High-speed transceiver circuitry is finding widespread use in the microelectronics and computer industries because of its superior traits over conventional bus technologies. These traits include, without limitation, improved throughput and wiring efficiencies. This circuitry, however, is analog in nature and is generally hard to design, characterize, and manufacture reliably. Accordingly, this unreliability creates challenges in the production test-phase. These challenges are forcing test professionals to revise their quality-assurance methodologies. These revisions, for example, include formulating new methodologies to screen modem high-speed transceiver designs because simple loop back testing is no longer sufficient.
Consequently, to properly screen high-speed transceiver designs, stressed-eye tests are required. These tests generate and introduce artificially induced jitter to a transceiver device, with the objective to measure the device's ability to resist the jitter. Notably, jitter-injection instruments for stressed-eye generation currently exist. These instruments, however, are rarely practical for production testing because of the instrument's high cost, limited number of channels, and the need for analog modulation circuitry. Moreover, delay-line techniques, used extensively for jitter injection, are unable to generate delay steps fine enough for the smallest delay element available in current high-speed transceiver designs. This deficiency may be overcome by using analog phase interpolation techniques, which allow for the generation of delay steps that are smaller than a unit delay element. These techniques, however, require careful tuning and are susceptible to process, manufacturing, and environmental conditions, and preclude the introduction of delay generators in digital-only or low-cost applications.